Semiconductor device having trench isolation

ABSTRACT

A semiconductor device having a trench isolation includes a trench formed in a surface of a semiconductor substrate and a buried insulating layer which fills the inside of the trench and has its top surface entirely located above the surface of the semiconductor substrate. A part of the buried insulating layer that protrudes from the surface of the semiconductor substrate has a projecting portion which is located on the surface of the semiconductor substrate and projects outward from a region directly above the trench. The projecting portion has a structure formed of at least two stacked insulating layers. Accordingly, the semiconductor device having the trench isolation can be provided by which a reverse narrow-channel effect can be suppressed and a reliable gate insulating layer can be obtained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device having atrench isolation. More specifically, the present invention relates to asemiconductor device having a trench isolation for electricallyisolating a semiconductor element from other semiconductor elements.

[0003] 2. Description of the Background Art

[0004] In recent years, as patterns for semiconductor devices haveincreased in density, a structure called shallow trench isolation (STI)has commonly been employed as an element isolation structure forelectrically isolating such a semiconductor element as field-effecttransistor from other semiconductor elements. This STI is disclosed forexample in Japanese Patent Laying-Open Nos. 2002-100671, 2002-93900 and11-67892.

[0005] An STI is fabricated for example through the following process.

[0006] On a semiconductor substrate, a thermal oxide film and a siliconnitride film are formed and a resist pattern is formed on the siliconnitride film. The resist pattern is used as a mask to anisotropicallyetch the silicon nitride film and the thermal oxide film and therebytransfer the resist pattern to the silicon nitride film and the thermaloxide film. The resist pattern is thereafter removed.

[0007] The silicon nitride film is then used as a mask toanisotropically etch the semiconductor substrate and thereby make atrench in the surface of the semiconductor substrate. Subsequently,thermal oxidation is performed to form a thermal oxide film on the innersurface of the trench. An oxide film is formed to fill the inside of thetrench and to cover the silicon nitride film. The oxide film is polishedaway by CMP (Chemical Mechanical Polishing) to expose the upper surfaceof the silicon nitride film. The silicon nitride film and the thermaloxide film are thereafter removed. In this way, an STI is completedhaving the trench in the surface of the semiconductor substrate that isfilled with the oxide film.

[0008] The recent increase in density of the pattern is accompanied by adecrease in width of an active layer. Therefore, influences of thereverse narrow-channel effect on transistors have become issues whichare not negligible. In addition, for flash memories, a reliable gateinsulating layer has become necessary since electrons pass through thegate insulating layer of the flash memories.

[0009] The above-described method of forming the STI, however, somewhatetches away the oxide film which fills the trench, in the step ofetching away the thermal oxide film. As a result, a depression isgenerated between the oxide film and the sidewall of the trench” On thisdepression, a gate insulating layer is formed and a gate electrode isformed on the gate insulating layer. Then, the issues of the reversenarrow-channel effect and deterioration in reliability of the gateinsulating layer are encountered to make it difficult to manufacturehigh-performance transistors and flash memories.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide a semiconductordevice having a trench isolation which can suppress the reversenarrow-channel effect and make a gate insulating layer reliable.

[0011] A semiconductor device having a trench isolation is, according tothe present invention, a semiconductor device having a trench isolationfor electrically isolating a semiconductor element from othersemiconductor elements, and the semiconductor device includes asemiconductor substrate and a buried insulating layer. The semiconductorsubstrate has a trench for the trench isolation in a main surface of thesemiconductor substrate. The buried insulating layer fills the inside ofthe trench and has its top surface entirely located above the mainsurface of the semiconductor substrate. A part of the buried insulatinglayer that protrudes from the main surface of the semiconductorsubstrate has a projecting portion which is located on the main surfaceof the semiconductor substrate and projects outward from a regiondirectly above the trench. The projecting portion has a structure formedof at least two stacked insulating layers.

[0012] The semiconductor device having the trench isolation according tothe present invention has the buried insulating layer which includes theprojecting portion located on the main surface of the semiconductorsubstrate and projects outward from the region directly above thetrench. Therefore, a depression of the buried insulating layer betweenthe buried insulating layer and the sidewall of the trench can beprevented from appearing. Accordingly, the reverse narrow-channel effectand the deterioration in reliability of the gate insulating layer due tothe depression can be prevented.

[0013] Further, as the projecting portion has the structure formed of atleast two stacked insulating layers, the two layers may be of differentmaterials respectively or the same material. The two layers may be ofdifferent materials respectively in such a manner that the material ofthe upper insulating layer is hard to remove in the step of removing thelower insulating layer. In this case, in the step of removing the lowerinsulating layer, it hardly occurs that a depression of the buriedinsulating layer appears between the buried insulating layer and thesidewall of the trench, so that a great margin can be ensured for theoccurrence of the depression in the removing step. Alternatively, thetwo layers may be of the same material and, in this case, the entireburied insulating layer can be of a single material so that parts of theburied insulating layer can be uniform in thermal expansion. Therefore,stress is unlikely to occur that is due to difference in thermalexpansion between the parts of the buried insulating layer.

[0014] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a cross-sectional view schematically showing a structureof a semiconductor device having a trench isolation according to a firstembodiment of the present invention.

[0016]FIG. 2 is a cross-sectional view schematically showing a structureof a semiconductor device having a trench isolation according to a thirdembodiment of the present invention.

[0017]FIGS. 3-11 are schematic cross-sectional views successivelyshowing steps of a manufacturing method of a semiconductor device havinga trench isolation according to a fourth embodiment of the presentinvention.

[0018]FIG. 12 is a schematic cross-sectional view showing a method ofmanufacturing a semiconductor device having a trench isolation accordingto a fifth embodiment of the present invention.

[0019]FIGS. 13-15 are schematic cross-sectional views successivelyshowing steps of a manufacturing method of a semiconductor deviceaccording to a sixth embodiment of the present invention.

[0020]FIG. 16 is a schematic cross-sectional view showing a method ofmanufacturing a semiconductor device having a trench isolation accordingto a seventh embodiment of the present invention.

[0021]FIGS. 17-21 are schematic cross-sectional views successivelyshowing steps of a manufacturing method of a semiconductor deviceaccording to an eighth embodiment of the present invention.

[0022]FIGS. 22 and 23 are schematic cross-sectional views successivelyshowing steps of a method of manufacturing a semiconductor device havinga trench isolation according to a ninth embodiment of the presentinvention.

[0023]FIGS. 24 and 25 are schematic cross-sectional views successivelyshowing steps of a method of manufacturing a semiconductor device havinga trench isolation according to a tenth embodiment of the presentinvention.

[0024]FIGS. 26 and 27 are schematic cross-sectional views successivelyshowing steps of a method of manufacturing a semiconductor device havinga trench isolation according to an eleventh embodiment of the presentinvention.

[0025]FIG. 28 is a schematic plan view showing the trench isolation ofthe first embodiment shown in FIG. 1 that electrically isolates a MOStransistor from other elements.

[0026]FIG. 29 is a schematic cross-sectional view along line XXIX-XXIXin FIG. 28.

[0027]FIG. 30 is a schematic cross-sectional view along line XXX-XXX inFIG. 28.

[0028]FIG. 31 is a schematic plan view showing the trench isolation ofthe first embodiment shown in FIG. 1 that electrically isolates a flashmemory from other elements.

[0029]FIG. 32 is a schematic cross-sectional view along line XXXI-XXXIIin FIG. 31.

[0030]FIG. 33 is a cross-sectional view of the first to the eleventhembodiments showing the dimension of each part of the trench isolation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Embodiments of the present invention are hereinafter described inconjunction with the drawings.

[0032] First Embodiment

[0033] Referring to FIG. 1, a semiconductor device according to thisembodiment has a trench isolation for electrically isolating asemiconductor element from other semiconductor elements. The trenchisolation includes a trench 2 formed in the surface of a semiconductorsubstrate 1 of silicon for example to serve for the trench isolation,and a buried insulating layer 3 filling the inside of this trench 2 andthus is buried therein. Buried insulating layer 3 fills the inside oftrench 2 and protrudes from the surface of semiconductor substrate 1.The protruded part has a projecting portion which is located on thesurface of semiconductor substrate 1 and projects in the outwarddirection (direction parallel to the surface of the semiconductorsubstrate) from a region located directly above trench 2. The projectingportion has a structure formed of at least two stacked insulatinglayers. The whole top surface of buried insulating layer 3 is locatedabove the surface of semiconductor substrate 1.

[0034] More specifically, buried insulating layer 3 has insulatinglayers 3 a, 3 b and 3 c. Insulating layer 3 b has insulating layers 3 b₁ and 3 b ₂. Insulating layer 3 b ₁ is formed along the inner surface(the sidewall and the bottom surface) of trench 2. Insulating layer 3 ais formed to fill the inside of trench 2 and protrude from the surfaceof semiconductor substrate 1. Insulating layer 3 a has a substantiallyflat top surface. Insulating layers 3 b ₂ and 3 c are formed to coverthe sidewall of the protruding part of insulating layer 3 a andaccordingly constitute the projecting portion. Insulating layer 3 b ₂abuts on the surface of semiconductor substrate 1 and insulating layer 3c is formed on insulating layer 3 b ₂.

[0035] According to this embodiment, buried insulating layer 3 has theprojecting portion which is located on the surface of semiconductorsubstrate 1 and projects outward from the region directly above trench2, so that a depression of buried insulating layer 3 that could appearbetween buried insulating layer 3 and the sidewall of trench 2 isprevented from occurring. Thus, occurrence of the reverse narrow-channeleffect and deterioration in reliability of the gate insulating layer,due to occurrence of the depression, can be prevented.

[0036] Moreover, as the projecting portion has the structure formed ofat least two stacked insulating layers 3 b ₂ and 3 c, these two layers 3b ₂ and 3 c may be of different materials respectively or the samematerial. Two layers 3 b ₂ and 3 c may be of different materialsrespectively in such a manner that the material of the upper insulatinglayer 3 c is hard to remove in the step of removing the lower insulatinglayer 3 b ₂. In this case, in the step of removing the lower insulatinglayer 3 b ₂, it hardly occurs that a depression of buried insulatinglayer 3 appears between buried insulating layer 3 and the sidewall oftrench 2, so that a large margin can be ensured for the occurrence ofthe depression in the removing step. Alternatively, these two layers 3 b₂ and 3 c may be of the same material and, in this case, buriedinsulating layer 3 can entirely be of a single material so that parts ofburied insulating layer 3 can be uniform in thermal expansion.Therefore, stress is unlikely to occur that is due to differences inthermal expansion between the parts of buried insulating layer 3.

[0037] Further, the entire top surface of insulating layer 3 a issubstantially flat, which makes it easy to pattern a gate electrode of,for example, a MOS transistor formed on the insulating layer.

[0038] Second Embodiment

[0039] Referring to FIG. 1, a semiconductor device of this embodimenthas a projecting portion formed of insulating layers 3 b ₂ and 3 c thatare different silicon oxide films. Insulating layer 3 b ₂ is made of asilicon oxide film formed by thermal oxidation (hereinafter referred toas thermal oxide film) while insulating layer 3 c is made of a siliconoxide film formed by a method different from the thermal oxidation, forexample, a silicon oxide film formed by HDP (High Density Plasma, thefilm hereinafter referred to as HDP oxide film), or a silicon oxide filmformed by TEOS (Tetra-Ethyl-Ortho-Silicate, the film hereinafterreferred to as TEOS oxide film). Therefore, insulating layer 3 b ₂ andinsulating layer 3 c are different in quality.

[0040] Insulating layer 3 a is made of, for example, an HDP oxide filmand insulating layer 3 b ₁ is made of, for example, a thermal oxidefilm.

[0041] Although insulating layer 3 a and insulating layer 3 c may beformed of different layers, they may be formed of the same layer. Inaddition, insulating layer 3 b ₁ and insulating layer 3 b ₂ may beformed of different layers while they may be formed of the same layer.

[0042] It is noted that details of the structure of this embodimentexcept for the above described ones are substantially the same ascorresponding ones of the first embodiment, like components are thusdenoted by like reference characters and description thereof is notrepeated here.

[0043] According to this embodiment, insulating layer 3 b ₂ andinsulating layer 3 c are both made of the silicon oxide films so as toallow the whole of buried insulating layer 3 to be formed of the siliconoxide films. If different materials are used to form respective parts ofburied insulating layer 3, stress arises due to a difference in thermalexpansion of the materials, for example. According to this embodiment,however, there is no influence of the stress due to such a difference inthermal expansion, since the whole of buried insulating layer 3 can beformed of the silicon oxide films.

[0044] Moreover, insulating layer 3 b ₂ formed directly on the surfaceof semiconductor substrate 1 is a thermal oxide film having lessimpurities as compared with an oxide film formed by CVD (Chemical VaporDeposition) for example, which is unlikely to adversely influencecharacteristics of a semiconductor device formed on the semiconductorsubstrate.

[0045] Third Embodiment

[0046] Referring to FIG. 2, a structure of this embodiment differs fromthat of the second embodiment in that insulating layers 3 b ₂ and 3 dforming the projecting portion of buried insulating layer 3 are made ofdifferent materials. Insulating layer 3 b ₂ is made of a thermal oxidefilm while insulating layer 3 d is made of a silicon nitride film.

[0047] Insulating layer 3 a is made of a silicon oxide film and thusinsulating layer 3 a and insulating layer 3 d are made of differentmaterials.

[0048] It is noted that details of the structure of this embodimentexcept for the above described ones are substantially the same ascorresponding ones of the second embodiment, like components are thusdenoted by like reference characters and description thereof is notrepeated here.

[0049] According to this embodiment, insulating layer 3 d is made of thesilicon nitride film which is hardly etched away in the step ofwet-etching insulating layer 3 b ₂ by using an HF (hydrofluoricacid)—based solution. Therefore, it is more unlikely, compared with thesecond embodiment, that a depression of buried insulating layer 3 occursbetween of buried insulating layer 3 and the sidewall of trench 2. Inthis way, a large margin for the occurrence of the depression in theetching step as mentioned above can be ensured.

[0050] Moreover, insulating layer 3 b ₂ formed directly on the surfaceof semiconductor substrate 1 is a thermal oxide film having lessimpurities as compared with an oxide film formed by CVD for example,which is unlikely to adversely influence characteristics of asemiconductor device formed on the semiconductor substrate.

[0051] Fourth Embodiment

[0052] This embodiment relates to a manufacturing method for the secondembodiment.

[0053] Referring to FIG. 3, on a surface of semiconductor substrate 1, athermal oxide film 3 b ₂ and a silicon nitride film 22 are successivelydeposited. A photoresist 23 is applied to silicon nitride film 22 and ispatterned by the usual photolithography technique to form resist pattern23.

[0054] Referring to FIG. 4, resist pattern 23 is used as a mask toanisotropically etch silicon nitride film 22 and thermal oxide film 3 b₂. Resist pattern 23 is thus transferred to silicon nitride film 22 andthermal oxide film 3 b ₂ to make a hole 30 which partially exposes thesurface of semiconductor substrate 1. Resist pattern 23 is thereafterremoved by, for example, ashing.

[0055] Referring to FIG. 5, the removal of resist patter 23 then exposesthe top surface of silicon nitride film 22.

[0056] Referring to FIG. 6, silicon nitride film 22 is used as a mask toanisotropically etch semiconductor substrate 1. In this way, trench 2for the trench isolation is formed in the surface of semiconductorsubstrate 1.

[0057] Referring to FIG. 7, immediately after trench 2 is formed,silicon nitride film 22 is wet-etched by means of a chemical solution ofhot phosphoric acid for example that dissolves the silicon nitride film.Accordingly, the thickness of silicon nitride film 22 decreases and thedimension of the opening D1 of hole 30 in silicon nitride film 22 isgreater than the dimension of opening D21 of hole 30 in thermal oxidefilm 3 b ₂.

[0058] Referring to FIG. 8, the inner surface of trench 2 is oxidized bythermal oxidation to form thermal oxide film 3 b ₁ along the innersurface of trench 2. This thermal oxide film 3 b ₁ extending along theinner surface of trench 2 and thermal oxide film 3 b ₂ formed on the topsurface of semiconductor substrate 1 form oxide film 3 b.

[0059] Referring to FIG. 9, silicon oxide film 3 a of, for example, HDPoxide film is deposited to fill trench 2 and hole 30 and to coversilicon nitride film 22.

[0060] Referring to FIG. 10, silicon oxide film 3 a is polished away byCMP until the top surface of silicon nitride film 22 is exposed.Accordingly, silicon oxide film 3 a is left within trench 2 and hole 30and respective top surfaces of silicon nitride film 22 and silicon oxidefilm 3 a are planarized. Silicon nitride film 22 and thermal oxide film3 b on an active region are thereafter removed.

[0061] Referring to FIG. 11, the removal of silicon nitride film 22 andthermal oxide film 3 b leaves buried insulating layer 3 formed ofthermal oxide film 3 b and silicon oxide film 3 a and thereby the trenchisolation of this embodiment is completed.

[0062] In this embodiment, silicon oxide film 3 a of buried insulatinglayer 3 corresponds to a combination of insulating layers 3 a and 3 c ofburied insulating layer 3 shown in FIG. 1.

[0063] According to this embodiment, in the step shown in FIG. 10,silicon oxide film 3 a is formed in advance to project outward (in thelateral direction as seen in FIG. 10), to a considerable degree, fromthe region directly above trench 2. Therefore, although silicon oxidefilm 3 a is removed to a certain degree in the step of removing thermaloxide film 3 b shown in FIG. 11, the projecting portion of silicon oxidefilm 3 a is left. Silicon oxide film 3 a can thus be prevented frombeing laterally etched away to the extent that the projecting portion ofsilicon oxide film 3 a disappears. Therefore, a depression of buriedinsulating layer 3 that could appear between the buried insulating layerand the sidewall of trench 2 can also be prevented. In this way,occurrence of the reverse narrow-channel effect as well as deteriorationin reliability of the gate insulating layer due to the depression can beprevented.

[0064] Moreover, according to this embodiment, only the wet-etching stepfor silicon nitride film 22 shown in FIG. 7 is added as compared withthe conventional manufacturing process so that an increase of the numberof steps can also be avoided.

[0065] Fifth Embodiment

[0066] This embodiment relates to a manufacturing method for the secondembodiment.

[0067] Initial steps of the manufacturing method of this embodiment aresimilar to those of the fourth embodiment shown respectively in FIGS.3-6. After this, referring to FIG. 12, the inner surface of trench 2 isoxidized by the thermal oxidation method to form thermal oxide film 3 b₁ along the inner surface of trench 2. Oxide film 3 b formed of thermaloxide film 3 b ₁ extending along the inner surface of trench 2 andthermal oxide film 3 b ₂ formed on the top surface of semiconductorsubstrate 1 is thus completed.

[0068] Referring to FIG. 8, immediately after the above-describedthermal oxide film 3 b ₁ is formed, silicon nitride film 22 iswet-etched by a chemical solution of hot phosphoric acid for examplethat dissolves the silicon nitride film. Accordingly, the thickness ofsilicon nitride film 22 decreases, and the dimension D1 of the openingof silicon nitride film 22 in hole 30 is greater than the dimension D22of the opening of oxide film 3 b in hole 30.

[0069] After this, according the manufacturing method of thisembodiment, similar steps to those of the fourth embodiment shownrespectively in FIGS. 9-11 are carried out to complete a trenchisolation of this embodiment.

[0070] According to this embodiment, an effect similar that of thefourth embodiment can be achieved. Moreover, the wet etching step forsilicon nitride film 22 is done in the state where the inner surface oftrench 2 is covered with oxide film 3 b ₁ in the steps shown in FIGS. 7and 8, and thus it is possible to prevent the etching solution frombeing brought into direct contact with the surface of semiconductorsubstrate 1.

[0071] Sixth Embodiment

[0072] This embodiment relates to a manufacturing method for the secondembodiment.

[0073] Referring to FIG. 13, the manufacturing method of this embodimentchiefly differs from that of the fourth embodiment in that a film 25containing silicon is formed between thermal oxide film 3 b ₂ andsilicon nitride film 22. A polycrystalline silicon film for example isformed as this film 25 containing silicon. After thermal oxide film 3 b₂, polycrystalline silicon film 25 and silicon nitride film 22 areformed, hole 30 and trench 2 are made as done in the fourth embodiment.

[0074] Referring to FIG. 14, as done in the fourth embodiment, siliconnitride film 22 is wet-etched by a chemical solution of hot phosphoricacid or the like that dissolves the silicon nitride film. Accordingly,the thickness of silicon nitride film 22 decreases, and the dimension D1of the opening of silicon nitride film 22 in hole 30 is greater than thedimension D23 of polycrystalline silicon film 25 and thermal oxide film3 b ₂ that are located in hole 30.

[0075] Referring to FIG. 15, the inner surface of trench 2 and a part ofpolycrystalline silicon film 25 are oxidized by the thermal oxidizationmethod. Thermal oxide film 3 b ₁ along the inner surface of trench 2 aswell as thermal oxide film 3 b ₃ which is the oxidized part ofpolycrystalline silicon film 25 are formed. These thermal oxide films 3b ₁, 3 b ₂ and 3 b ₃ thus form oxide film 3 b.

[0076] According to the manufacturing method of this embodiment, throughthe following steps that are similar to those of the fourth embodimentshown respectively in FIGS. 9-11, a trench isolation of this embodimentis completed.

[0077] According to this embodiment, an effect similar to that of thefourth embodiment can be achieved. Moreover, silicon-containing film 25is formed as a buffer layer. Then, the phase state and the concentrationof impurities, for example, of this silicon-containing film 25 may bechanged to facilitate control of the manner in which silicon-containingfilm 25 is oxidized in the thermal oxidation step. Consequently, theoccurrence of the depression of buried insulating layer 3, that couldappear between buried insulating layer 3 and the sidewall of trench 2,is more easily prevented.

[0078] Seventh Embodiment

[0079] This embodiment relates to a manufacturing method for the secondembodiment.

[0080] The manufacturing method of this embodiment chiefly differs fromthat of the fifth embodiment in that a film 25 containing silicon isformed between thermal oxide film 3 b ₂ and silicon nitride film 22.

[0081] According to this embodiment, a step similar to that of the sixthembodiment shown in FIG. 13 is carried out. Referring to FIG. 16, theinner surface of trench 2 and a part of polycrystalline silicon film 25are thereafter oxidized by the thermal oxidation method. Accordingly,thermal oxide film 3 b ₁ along the inner surface of trench 2 as well asthermal oxide film 3 b ₃ which is the oxidized part of polycrystallinesilicon film 25 are formed. These thermal oxide films 3 b ₁, 3 b ₂ and 3b ₃ form oxide film 3 b.

[0082] Referring to FIG. 15, immediately after thermal oxide films 3 b ₁and 3 b ₃ are formed, silicon nitride film 22 is wet-etched by achemical solution of hot phosphoric acid or the like that dissolves thesilicon nitride film. Accordingly, the thickness of silicon nitride film22 decreases, and the dimension D1 of the opening of silicon nitridefilm 22 in hole 30 is greater than the dimension D24 of oxide film 3 blocated in hole 30.

[0083] According to the manufacturing method of this embodiment, throughthe following steps that are similar to those of the fourth embodimentshown respectively in FIGS. 9-11, a trench isolation of this embodimentis completed.

[0084] According to this embodiment, an effect similar to that of thefifth embodiment can be achieved. Moreover silicon-containing film 25 isformed as a buffer layer. Then, the phase state and the concentration ofimpurities, for example, of this silicon-containing film 25 may bechanged to facilitate control of the manner in which silicon-containingfilm 25 is oxidized in the thermal oxidation step. Consequently, theoccurrence of the depression of buried insulating layer 3, that couldappear between buried insulating layer 3 and the sidewall of trench 2,is more easily prevented.

[0085] Eighth Embodiment

[0086] This embodiment relates to a manufacturing method for the secondembodiment.

[0087] The manufacturing method of this embodiment follows the stepsrespectively shown in FIGS. 3-6 and then the step shown in FIG. 12.

[0088] Referring to FIG. 17, silicon oxide film 3 a formed of an HDPoxide film, for example, is thereafter formed to fill trench 2 and hole30 and cover silicon nitride film 22.

[0089] Referring to FIG. 18, silicon oxide film 3 a is polished away byCMP until the top surface of silicon nitride film 22 is exposed.Accordingly, silicon oxide film 3 a is left within trench 2 and hole 30,and respective top surfaces of silicon nitride film 22 and silicon oxidefilm 3 a are planarized. After this, silicon nitride film 22 and thermaloxide film 3 b ₂ on an active region are removed.

[0090] Referring to FIG. 19, the removal of silicon nitride film 22 andthermal oxide film 3 b ₂ temporarily exposes the surface ofsemiconductor substrate 1, while thermal oxide film 3 b ₁ and siliconoxide film 3 a are left in trench 2. After this, the exposed surface ofsemiconductor substrate 1 is oxidized by the thermal oxidation method toform thermal oxide film 3 b ₂.

[0091] Referring to FIG. 20, TEOS oxide film 3 c is formed to coversilicon oxide film 3 a and thermal oxide film 3 b ₂. After this, theentire surface is anisotropically etched (etched back) until the surfaceof semiconductor substrate 1 is partially exposed.

[0092] Referring to FIG. 21, the etch-back process leaves thermal oxidefilm 3 b ₂ and TEOS oxide film 3 c only on the lateral side of a part ofsilicon oxide film 3 a that protrudes from the surface of semiconductorsubstrate 1. In this way, buried insulating layer 3 formed of siliconoxide film 3 a, thermal oxide films 3 b ₁ and 3 b ₂ and TEOS oxide film3 c is produced. Of these oxide films, thermal oxide film 3 b ₂ and TEOSoxide film 3 c form a projecting portion. A trench isolation of thisembodiment is accordingly completed.

[0093] According to this embodiment, TEOS oxide film 3 c is formed onthe entire surface that is then etched back, so that a depression of thesilicon oxide film that could appear between silicon oxide film 3 a andthe sidewall of trench 2 can be filled and the projecting portion ofburied insulating layer 3 can be formed. Thus, it is achieved to preventoccurrence of the reverse narrow channel effect as well as deteriorationin reliability of the gate insulating layer that are caused due to thepresence of the depression.

[0094] Ninth Embodiment

[0095] This embodiment relates to a manufacturing method for the secondembodiment.

[0096] The manufacturing method of this embodiment initially follows thesteps similar to those of the eighth embodiment to the step shown inFIG. 20. After this, the entire surface of TEOS oxide film 3 c isanisotropically etched to the degree that the surface of thesemiconductor substrate 1 is not exposed.

[0097] Referring to FIG. 22, the etch-back step leaves thermal oxidefilm 3 b ₂ and a part of TEOS oxide film 3 c on the surface ofsemiconductor substrate 1. The silicon oxide film is thereafterwet-etched until a part of the surface of semiconductor substrate 1 isexposed.

[0098] Referring to FIG. 23, the wet-etching step leaves thermal oxidefilm 3 b ₂ and a TEOS oxide film 3 c only on the lateral side of a partof silicon oxide film 3 a that protrudes from the surface ofsemiconductor substrate 1. Accordingly, buried insulating layer 3 whichis formed of silicon oxide film 3 a, thermal oxide films 3 b ₁ and 3 b ₂and TEOS oxide film 3 c is completed. Of these oxide films, thermaloxide film 3 b ₂ and TEOS oxide film 3 c form a projecting portion. Atrench isolation of this embodiment is thus completed.

[0099] According to this embodiment, a similar effect to that of theeighth embodiment can be achieved. Moreover, a plasma-caused damage onthe surface of semiconductor substrate 1 can be avoided sincesemiconductor substrate 1 does not undergo the dry-etching in theetch-back step.

[0100] Tenth Embodiment

[0101] This embodiment relates to a manufacturing method for the thirdembodiment.

[0102] The manufacturing method of this embodiment follows the stepssimilar to those of the eighth embodiment to the step shown in FIG. 19.Referring to FIG. 24, silicon nitride film 3 d is thereafter formed tocover silicon oxide film 3 a and thermal oxide film 3 b ₂. Then, theentire surface of silicon nitride film 3 d is anisotropically etched(etched back) until a part of the surface of semiconductor substrate 1is exposed.

[0103] Referring to FIG. 25, the etch-back step leaves thermal oxidefilm 3 b ₂ and silicon nitride film 3 d only on the lateral side of apart of silicon oxide film 3 a that protrudes from the surface ofsemiconductor substrate 1. Accordingly, buried insulating layer 3 formedof silicon oxide film 3 a, thermal oxide films 3 b ₁ and 3 b ₂ andsilicon nitride film 3 d is produced. Thermal oxide film 3 b ₂ andsilicon nitride film 3 d form a projecting portion of buried insulatinglayer 3. A trench isolation of this embodiment is thus completed.

[0104] According to this embodiment, silicon nitride film 3 d is formedon the entire surface that is then etched back, so that a depression ofthe silicon oxide film that could appear between silicon oxide film 3 aand the sidewall of trench 2 can be filled and the projecting portion ofburied insulating layer 3 can be formed. Thus, it is achieved to preventoccurrence of the reverse narrow channel effect as well as deteriorationin reliability of the gate insulating layer that are caused due to thepresence of the depression.

[0105] Moreover, since insulating layer 3 b ₂ formed directly on thesurface of semiconductor substrate 1 is the thermal oxide film which issmaller in the number of impurities as compared with an oxide filmformed by the CVD or the like, it hardly occurs that characteristics ofa semiconductor element formed on the semiconductor substrate areadversely affected.

[0106] Eleventh Embodiment

[0107] This embodiment relates to a manufacturing method for the thirdembodiment.

[0108] The manufacturing method of this embodiment follows the stepssimilar to those of the tenth embodiment to the step shown in FIG. 24.After this, the entire surface of silicon nitride film 3 d isanisotropically etched (etched back) until a part of thermal oxide film3 b ₂ is exposed.

[0109] Referring to FIG. 26, the etch-back step leaves silicon nitridefilm 3 d only on the lateral side of a part of silicon oxide film 3 athat protrudes from the surface of semiconductor substrate 1. Afterthis, the silicon oxide film is wet-etched by an HF (hydrofluoricacid)—based solution until a part of the surface of semiconductorsubstrate 1 is exposed.

[0110] Referring to FIG. 27, the wet-etching step leaves thermal oxidefilm 3 b ₂ only on the lateral side of the part of silicon oxide film 3a that protrudes from the surface of semiconductor substrate 1 and undersilicon nitride film 3 d. Accordingly, buried insulating layer 3 formedof silicon oxide film 3 a, thermal oxide films 3 b ₁ and 3 b ₂ andsilicon nitride film 3 d is produced. Thermal oxide film 3 b ₂ andsilicon nitride film 3 d form a projecting portion of buried insulatinglayer 3. A trench isolation of this embodiment is thus completed.

[0111] According to this embodiment, a similar effect to that of thetenth embodiment can be achieved. Moreover, since semiconductorsubstrate 1 is not subjected to the dry-etching in the etch-back step, aplasma-caused damage on the surface of semiconductor substrate 1 can beavoided.

[0112] In addition, the silicon nitride film is hardly etched away inthe wet-etching step for thermal oxide film 3 b ₁ by means the of HF(hydrofluoric acid)—based solution. Then, it hardly occurs that adepression of buried insulating layer 3 appears between buriedinsulating layer 3 and the sidewall of trench 2, as compared with thetenth embodiment, so that a great margin can be ensured for occurrenceof the depression in the etching step.

[0113] It is noted that respective trench isolations of the first toeleventh embodiments are used for electrically isolating a semiconductorelement from other semiconductor elements. A description is now givenbelow of the way in which the trench isolation of the first embodimentshown in FIG. 1 electrically isolates a MOS transistor, for example,from other elements.

[0114] Referring to FIGS. 28-30, a trench isolation formed of trench 2which is made in the surface of semiconductor substrate 1 and buriedinsulating layer 3 which fills the inside of trench 2 is formed tosurround an active region. A MOS transistor 10 is formed in this activeregion.

[0115] MOS transistor 10 has a pair of source/drain regions 11, a gateoxide film 12 and a gate electrode 13. The paired source/drain regions11 are formed in the surface of the active region and spaced from eachother. Gate electrode 13 is formed on a region sandwiched between pairedsource/drain regions 11 with gate oxide film 12 therebetween.

[0116] Gate electrode 13 extends in one direction across the activeregion, for example. In this case, gate electrode 13 extends overprojecting portions 3 b and 3 c of buried insulating layer 3. If aninterlayer insulating layer (not shown) is formed to cover MOStransistor 10, this interlayer insulating layer is also formed onprojecting portions 3 b and 3 c of buried insulating layer 3. In otherwords, on projecting portions 3 b and 3 c of buried insulating layer 3,a conductive layer and an insulating layer are formed at upper levels.

[0117] The trench isolation thus surrounds the region where MOStransistor 10 is formed so as to electrically isolate MOS transistor 10from other semiconductor elements.

[0118] A description is now given below of the way in which the trenchisolation of the first embodiment shown in FIG. 1 electrically isolatesa flash memory, for example, from other elements.

[0119] Referring to FIGS. 31 and 32, a trench isolation formed of trench2 made in the surface of semiconductor substrate 1 and buried insulatinglayer 3 which fills the inside of trench 2 is formed to surround anactive region. In this active region, a flash memory 50 is formed.

[0120] Flash memory 50 has a pair of source/drain regions 51, a gateinsulating film 52, a floating gate electrode 53, and a control gateelectrode 54. Although an insulating film is formed between floatinggate electrode 53 and control gate electrode 54 for electricallyinsulating floating gate electrode 53 and control gate electrode 54,this insulating film is not shown for convenience of description.

[0121] Paired source/drain regions 51 are formed in the surface of theactive region and spaced apart. On a region sandwiched between pairedsource/drain regions 51, floating gate electrode 53 is formed with gateinsulating film 52 therebetween. Control gate electrode 54 extends overfloating gate electrode 53 with the insulating film (not shown)therebetween.

[0122] Control gate electrode 54 extends in one direction across theactive region for example. In this case, control gate electrode 54extends over the projecting portion of buried insulating layer 3. If aninterlayer insulating layer (not shown) is formed to cover flash memory50, this interlayer insulating layer is also formed over the projectingportion of buried insulating layer 3. In other words, on the projectingportion of buried insulating layer 3, a conductive layer and aninsulating layer are formed at upper levels.

[0123] The trench isolation thus surrounds the region where flash memory50 is formed so as to electrically isolate flash memory 50 from othersemiconductor elements.

[0124] By electrically isolating flash memory 50 from other elements bythe trench isolation of this embodiment as described above, the width W1of the gate insulating film between buried insulating layers 3 can bemade smaller than the width W2 of the active region between trenches 2because of the presence of the projecting portion of buried insulatinglayer 3. Accordingly, the area of gate insulating film 52 facing thesurface of semiconductor substrate 1 can be made smaller. The couplingcapacitance thus increases (a relative difference in potential betweenfloating gate electrode 53 and semiconductor substrate 1 increases) toimprove the efficiency in erasure and writing of data of flash memory50.

[0125] Although the MOS transistor and the flash memory have beendescribed, the present invention is not limited to them and isapplicable to electrical isolation of other semiconductor elements.

[0126] Each part of the trench isolation in the first to eleventhembodiments has its dimension as described below.

[0127] Referring to FIG. 33, the width “a” of insulating layer 3 a intrench 2 is, for example, at least 0.10 μm and at most 0.30 μm, and thiswidth is determined depending on the limit at which the insulating layercan fill the whole of the trench. The dimension “b” of the projectingportion of buried insulating layer 3 is, for example, at least 20 nm andat most 50 nm, and this dimension is determined by the total amountetched after the projecting portion is formed. The thickness “c” ofinsulating layer 3 c of the projecting portion is, for example, at least20 nm and at most 50 nm, and this thickness is determined by the totalamount etched after the projecting portion is formed. The thickness “d”of insulating layer 3 b of the projecting portion is, for example, atleast 3 nm and at most 15 nm. Regarding this thickness “d,” a requiredthickness varies depending on the etch selectivity since insulatinglayer 3 b is to be covered with an oxide film.

[0128] It is preferable that the sum of the thickness “c” and thethickness “1 d” (“c+d”, i.e., the total thickness of the projectingportion) is, for example, at least 23 nm and at most 75 nm. If thedimension “c+d” is smaller than 23 nm, it could occur that insulatinglayer 3 c is not formed on semiconductor substrate 1 due to variationsin manufacture. If the dimension “c+d” is greater than 75 nm, there is agreat difference between the level of semiconductor substrate 1 andburied insulating layer 3, which makes it difficult to pattern a gateelectrode formed on buried insulating layer 3.

[0129] The angle “e” formed between the sidewall of the part ofinsulating layer 3 a that protrudes from semiconductor substrate 1 andthe surface of semiconductor substrate 1 may be, for example, at most1200 and preferably at most 90°. This angle between the sidewall ofinsulating layer 3 a and the surface of semiconductor substrate 1 may beany unless an extremely reverse-tapered shape is formed by the anglewhich causes a thin film not to be formed by CVD on the sidewall ofinsulating layer 3 a.

[0130] It is noted that FIG. 33 shows no hatching for clearly showingthe dimensions.

[0131] The dimension of each part is one preferable dimension which doesnot limit the present invention to the particular dimension.

[0132] It has been described with regard to the first to eleventhembodiments that the two layers that are components of the projectingportion of buried insulating layer 3 are silicon oxide films or acombination of a silicon oxide film and a silicon nitride film. Othermaterials, however, may be employed for these components. In addition,the number of layers of the projecting portion is not limited to two,and the projecting portion may be formed of three or more layers.Further, insulating layer 3 a of the fourth to seventh embodiments maybe a silicon nitride film.

[0133] Although the present invention has been described and illustratedin detail, it is dearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor device having a trench isolationfor electrically isolating a semiconductor element from othersemiconductor elements, comprising: a semiconductor substrate having atrench for said trench isolation that is located in a main surface ofsaid semiconductor substrate; and a buried insulating layer filling theinside of said trench and having its top surface entirely located abovethe main surface of said semiconductor substrate; a part of said buriedinsulating layer that protrudes from the main surface of saidsemiconductor substrate having a projecting portion which is located onthe main surface of said semiconductor substrate and projects outwardfrom a region directly above said trench, and said projecting portionhaving a structure formed of at least two stacked insulating layers. 2.The semiconductor device having the trench isolation according to claim1, wherein said projecting portion has a structure formed of a firstoxide film and a second oxide film that are stacked.
 3. Thesemiconductor device having the trench isolation according to claim 1,wherein said projecting portion has a structure formed of an oxide film-and a nitride film that are stacked.
 4. The semiconductor device havingthe trench isolation according to claim 1, wherein said projectingportion has a thickness of at least 23 nm and at most 75 nm.
 5. Thesemiconductor device having the trench isolation according to claim 1,further comprising a gate insulating film formed on the main surface ofsaid semiconductor substrate, wherein said gate insulating film has itswidth, defined in a cross section of said semiconductor device, betweenone portion and the other portion of said buried insulating layer, anactive region has its width defined in said cross section between oneportion and the other portion of said trench, and the width of said gateinsulating film is smaller than the width of said active region.